The present invention is related to memory architectures and, more particularly, to architectures for compression and encryption of memory.
Compression and encryption techniques are well-known. A recent development has been to use techniques such as compression to reduce the size of main memory in a computer architecture. See, e.g., M. Kjelso et al., “Main Memory Hardware Data Compression,” 22nd Euromicro Conference, pages 423-30, IEEE Computer Society Press (September 1996). For example, researchers at IBM have developed the “MXT” architecture for servers which performs compression and decompression during runtime of an application when transferring data from the L3 cache to main memory and vice versa. See Tremaine et al., “IBM Memory Expansion Technolog (MXT),” IBM J. Res. & Dev., Vol. 45, No. 2 (March 2001). See also U.S. Pat. Nos. 5,761,536, 5,812,817, and 6,240,419, which are incorporated by reference herein. Similarly, encryption has been utilized in the prior art to protect sensitive code or data stored in memory.
Despite the advances in compression and encryption, prior art use of application compression and encryption techniques typically rely on the following constraints. First, compression/decompression and encryption/decryption is typically applied at a specific level of the memory hierarchy. Second, once that level of the memory hierarchy is pre-specified, a specific compression and/or encryption algorithm is selected, namely an algorithm that is suitable for that level of the memory hierarchy. Thus, solutions currently available will provide a compression or encryption scheme that may be optimal with regards to a portion of an application's code or data but that may be suboptimal with regards to much of the rest of the application code or data. This is particularly of concern in embedded systems, where space constraints and security issues typically exist.
Accordingly, there is a need for an architecture that can handle compression and encryption in a more flexible and efficient manner.